IC Package Design
Caliber offer IC package design services for package design technologies such as flip-chip, wire-bond, stacked-die, System-in-Package (SiP), Package-on-Package (PoP), Package-in-Package (PiP), Chip-Scale-Package (CSP) and other vertical space transformers (MLO/MLC) meant for ATE testing applications. We offer package solutions for high - speed digital ICs, mixed-signal ICs and RFIC products.
Package design has become very complex with ever increasing data - rates and shrinking IC fabrication process technology (40nm, 28nm, 20nm, 12nm etc). This requires high degree of expertise and careful signal integrity & power integrity analysis within IC/Package co - design environment. We have strong capability to perform simultaneous - switching - noise (SSN) SI/PI simulations, package parasitic extractions, System level SI timing analysis and Power integrity optimization using latest Ansys and Cadence sigrity tools. We also take care of thermal and mechanical aspect of package design.
- Flip-Chip BGA, Wire-bond BGA, Chip-Scale-Package (CSP), Package-on-Package (PoP), Package-in-Package (PiP) design, MLO/MLC package for ATE hardware.
- System-in-Package (SiP) design for applications such as Cellular, Bluetooth, WLAN, GPS, Camera, PDA and CMOS sensor.
- Signal Integrity & Power Integrity analysis & optimization during early stage of package design.
- IC/Package/board co - design flow.
- Strong interaction with all stakeholders in package design process.
- SSN analysis based on SI/PI co - design flow using SPICE netlist.
- Package RLC extraction & package model generation for SI/PI analysis.
- Power Integrity and decoupling cap optimization.
- Design tools – Mentor Package designer and Allegro Package designer.
- Thermal & Mechanical design.
- Co - ordination with assembly-house and substrate foundry to achieve first time right substrate.
- Strict adherence to assembly specifications.
- Experienced CAM team validates the design for Fab house DFM specification.
Leading provider of high speed design and analysis services for:
- Probe Cards.
- System in Packages(SiP).
- Multi Layer Package Designs and Layouts.
- Multi Chip Modules(MCMs).
- MLO/MLC Substrate Designs.
Highly Skilled Design/Analysis and Layout Team:
- More than 800+ package designs successfully completed.
- Organic build up from 1-2-1 to 8-2-8 layers.
- Low Cost 4 layer Laminates.
- Multi layer Ceramic designs.
- Experience in wirebond and flip chip design and layout techniques.
- Chip Scale Package designs.
Cost Effective and Timely Job completion
Lead Time 1.5 weeks to 3 weeks from frozen netlist based on complexity.